Senior Mask Layout Design Engineer

Last updated one month ago
Location:Raleigh, North Carolina
Job Type:Full Time

Microsoft Silicon Team is continuing to revolutionize consumer electronic devices & Cloud Computing.

This group designs high performance mixed signal ASICs in leading edge CMOS technology using custom IC design tools. You will work in a diverse, dynamic environment and interact with other teams to help design and test great products!

The ideal candidate is a self-starter, highly motivated engineer with excellent technical & interpersonal skills, used to working independently or as a key member of a fast moving design team.


The primary responsibility of this position entails Leading and executing IC layout of cutting edge, high performance, high speed CMOS SERDES integrated circuits in foundry CMOS process nodes in 5nm, 7nm,16nm following industry best practices.

You will be responsible for all or parts of the following areas:

  • Using Cadence Virtuoso design tool and flow
  • Will be working on highly analog IPs like analog PLL, ADC, VGA, RX, TX, and Bias
  • Layout Design review presentations.
  • Layout floor-planning and supervision.
  • Physical LVS and DRC


  • You should have 5 plus years of experience in high performance analog layout in advanced CMOS process; BS degree a plus
  • Detailed knowledge of EDA tools for Cadence, Mentor and Synopsys.
  • Have experience with layout of high performance analog blocks such as analog to VCOs, chargepump, interpolators, bandgap, OTAs, PLLs, ADCs, LDOs, RX, TX, references, etc. is desired.
  • Knowledge with analog design and layout guidelines and high speed IO.
  • Experience with floor planning, block level routing and large macro level assembly.
  • Knowledge of high performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.
  • Confirmed experience with analog layout for silicon chips in mass production.
  • Worked with sub-micron design in foundry CMOS nodes 5nm and 7nm FINFET.
  • Requires self-starter with the ability to define and adhere to a schedule.

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.